搜索资源列表
DDR3
- DDR3控制器，基于Altera平台，修改管教后直接可以下载进PFGA-DDR3 controller, based on Altera platform, modify the discipline can be downloaded directly into the PFGA
52K_19200_1_2010.02.08.16.06.44_4247_KO[1].pdf.zi
- DDR3 SDRAM datasheet please refer want to development DDR3 Controller
ddr3_altera_use
- altera kit gx4 上DDR3 控制器的使用-altera kit gx4 on the use of DDR3 controller
94117c05d50c
- Its a clock Sequence for DDR3 Controller.Hope u find it useful
ddr3_controller1
- ddr3 controller for axi interface
DDR3_user_design
- 在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器，里面生成了Core，可用于DDR3读写控制-On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control
rdf0011
- 用VerilogHDL遍写的ddr3控制器，使用了自带的ip核生成mig来进行读写。-Times to write with VerilogHDL ddr3 controller, use the ip core generator that comes with mig to read and write.
DDR3-SDRAM-Controller
- DDR3的控制器（并带有Testbench），可烧录到FPGA中对内存进行读写，相关技术人员可在该代码上修改用于其他场合-DDR3 controller (with an Testbench), the FPGA can be burned to the memory read and write, the relevant technical staff can modify the code to be used on other occasions
vc707-mig-rdf0160-14.3
- 适用于DDR3 控制器代码等的FPGA代码-DDR3 controller code for FPGA code, etc.
DDRController
- DDR3控制器，用于FPGA内部对DDR进行操作，利用Avlone总线进行对接-DDR controller
DDR3-SDRAM-controller
- My package named design DDR3 Synchronous Data Random Access Memory by verilog.The memory controller is a digital circuit which manages the flow of data going to and from the computer s main memory.
lib_dmarc_1d_v1
- xilinx DDR3控制器读数据控制,对读控制器进行了很好的读写封装，可以支持连续和非连续读写。-xilinx DDR3 controller reads the data controller, the read controller package to read and write well, you can support continuous and sequential read and write.
ddr3_demo_verilog
- 基于Verilog HDL的ddr3控制器，适用于lattice的ECP3系列-ddr3 controller based on Verilog HDL，used in lattice ECP3 serial FPGA
DDR3-User-Guide
- 在DDR3内存控制器一起使用JESD79-3C符合标准SDRAM器件接口。内存类型，如DDR1 SDRAM，DDR2 SDRAM，SDR SDRAM，SBSRAM和异步不支持的回忆。在DDR3内存控制器，SDRAM，可用于程序和数据存储。梯形失真校正设备有一个实例。-Use JESD79-3C standard SDRAM DDR3 memory controller interface devices together. Memory types, such as DDR1 SDRAM, DD
DDR3_controller
- DDR3的控制器程序，可烧录到FPGA中对内存进行读写，可在该代码上修改用于其他场合。-DDR3 controller program, are programmed into the FPGA, memory read and write, you can modify the code used on other occasions.
mcb_traffic_gen
- 本文档为ddr3的控制器，可以实现DDR3的读写操作。-This document is ddr3 controller, DDR3 can achieve read and write operations.
mig_7series_v1_9
- DDR3控制器源码，针对XilinxFPGA的DDR3控制器的源码，已经验证通过。-DDR3 Controller，complete DDR3 controll，have pass verificaion.
02_ddr3_test
- Altera fpga ddr3 控制器测试模块(Altera FPGA DDR3 controller test module)
Verilog_1Gb_DDR3_G_Die
- ddr3控制器，速率可达1Gbps，语言使用verilog，已经加入tb(ddr3 controller, can be used to ddr3 control,high speed)
09_ddr3_test
- 利用vivado的MIG控制器来实现DDR3的读写(Using vivado's MIG controller to realize DDR3's read and write)